
module frv_regfile (
    input                       clk             ,
    input                       rst_n           ,
    input                       pd_rst          ,
    // Regfile Operation
    input [4:0]                 rf_rs1_ind      ,
    output[31:0]                rf_rs1_data     , // rs1 data
    input [4:0]                 rf_rs2_ind      ,
    output[31:0]                rf_rs2_data     , // rs2 data
    // Retire Interface
    input                       ret_rd_req      ,
    input [4:0]                 ret_rd_ind      ,
    input [31:0]                ret_rd_data      // commit index
);

logic[31:0] regs[31:1];

always_ff @(posedge clk)
    if(!rst_n) begin
        for (int i=1; i<32; i++) begin
            regs[i] <= 0;
        end
    end
    else if(ret_rd_req)
        regs[ret_rd_ind] <= ret_rd_data;

assign rf_rs1_data = rf_rs1_ind == 0 ? 0 : regs[rf_rs1_ind];

assign rf_rs2_data = rf_rs2_ind == 0 ? 0 : regs[rf_rs2_ind];

// `psv_begin
// for i range(1,32)
//     print("wire             rf_data_wen_%d;"%i);
//     print("wire[31:0]       rf_data_%d;"%(i,i));
// `psv_end

// //RF Read Operation
// assign rf_rs1_data = ({32{rf_rs1_ind == 1}} & rf_data_0) 
// `psv_begin
// for i range(1,32)
//     print("        | ({32{rf_rs1_ind == %d}} & rf_data_%d)"%(i,i));
// print("             ;\n");
// `psv_end

// assign rf_rs2_data = ({32{rf_rs2_ind == 1}} & rf_data_0) 
// `psv_begin
// for i range(1,32)
//     print("        | ({32{rf_rs2_ind == %d}} & rf_data_%d)"%(i,i));
// print("             ;\n");
// `psv_end

// //RF Write Operation
// `psv_begin
// for i range(1,32)
//     print("assign rf_data_wen_%d = ret_rd_req && ret_rd_ind == %d;"%(i,i));
// `psv_end

// `psv_begin
// for i range(1,32)
//     print("dffr #(32) rf_data_ff_%d (clk,rst_n,rf_data_wen_%d,ret_rd_data,rf_data_%d);"%(i.i,i));
// `psv_end

endmodule

